1. Field of the Invention
The invention generally relates to metal layer structures that comprise via holes and arrangements of metal lines for connecting metal layers, and in particular to a technique to identify a revision of the metal layer structure.
2. Description of the Related Art
Complex semiconductor devices and high-speed circuitry of today""s electronics are changing the role of the interconnection substrates. No longer does the substrate just provide a replacement for wires. The interconnecting substrate provides circuit signal matching, terminal management and mechanical support, as well as electrical functionality. These characteristics are needed to support the advancement made in semiconductor technology. The chip complexity increases with reduced chip sizes and reduced contact pitches, and represents challenges for both, the assemblers and board manufacturers. The assemblers have handling problems, coplanarity difficulties and alignment problems. The board manufacturers have to solve size problems, layout mask difficulties and electrical test problems. These high demands require multi-layer or high-density interconnection designs to support the wiring needs for closely spaced devices.
Multi-layer structures include, for instance, 4 to 8 layers and a multi-layer structure is built up in different manufacturing steps. A base of the multi-layer structure is a substrate. By applying e.g. a photosensitive polymer and then exposing the substrate to ultraviolet light through a layout mask that contains the desired circuits, a dielectric is developed and the result is a hard dielectric coating on the substrate containing a circuit pattern in the form of grooves. A conductive material is applied to fill the photo-exposed conductor grooves and holes. The circuit is then dried and cured. A second layer of photo-sensitive dielectric may be then applied and exposed to ultraviolet light through a layout mask containing a pattern for via holes. After developing, the via holes are filled with conductive materials and cured as before. A third layer of photo-sensitive dielectric is then applied. This layer is exposed, developed, filled and cured to provide the circuitry for the second conductor layer. This process can be repeated sequentially to produce a multi-layer structure.
The above-described manufacturing steps result, for instance, in a multi-layer structure as illustrated in FIG. 1. As can be seen, the multi-layer structure comprises several layers of dielectric material 110. To the dielectric layers metal layers 100 are applied that are vertically connected by via holes 120, 130. The via holes 120 may be arranged for vertically connecting an electronic device 140 that is embedded in the multi-layer structure, for instance to connect the electronic device 140 with the top metal layer.
The via holes of the structure illustrated in FIG. 1 are positioned according to requirements of the embedded electronic devices, and may further form a connection to certain points on a top metal layer to be bonded to contact pitches, or to provide at a certain metal layer a defined electrical potential.
Assuming, a metal layer structure layout has to be modified, for example to implement corrections of the metal line arrangement, an identification of the metal layer structure may be used to trace the applied modifications and to identify the revision number of the metal layer structure. Generally, the revision number of an integrated circuit chip is software readable, wherein for instance, a software read procedure reads the implemented revision number and may further initiate revision number specific actions. The implementation of such a revision identification technique requires high additional efforts to adapt the layers of the metal layer structure.
The conventional techniques of providing an identification for a metal layer structure may be expensive and disadvantageous because for each adaptation of the revision number it may be necessary to implement additional modifications of the layer structure in the layout mask for several layers. That is, even if the electrical connections of only one metal layer are to be modified for the purpose of correcting layout mistakes or for other reasons, the conventional technique often require to produce modified layout masks for further metal layers, just in order to update the revision number.
A further disadvantage of the conventional techniques may be a waste of chip area. Thus, the application of the conventional techniques result in unnecessarily complicated and cost intensive manufacturing.
An integrated circuit chip and a manufacturing method are provided that may have improved connectivity characteristics, and that may in particular be suitable for reducing the manufacturing costs when providing identification features.
In one embodiment, there is provided an integrated circuit chip that comprises a metal layer structure that has at least three substantially horizontal metal layers and a plurality of substantially vertical via holes. Each of the metal layers comprises at least one metal line. Each of the via holes electrically connects a metal line of one metal layer with a metal line of another metal layer. The integrated circuit chip further comprises a first tap that is located in a first one of the metal layers, and a second and third tap that are located in a second one of the metal layers. The metal lines and via holes form a signal path that electrically connects the first tap with the second tap. The metal lines in each metal layer are arranged in a respective first one of at least two predefined configurations. The at least two predefined configurations comprise for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with the third tap.
In a further embodiment, there is provided an integrated circuit chip that has a revision identification register that stores revision identification data, and an output port that is connected to the revision identification register to output the revision identification data. The revision identification register comprises a metal layer structure that has at least three substantially horizontal metal layers and a plurality of substantially vertical via holes. Each of the metal layers comprises at least one metal line. Each of the via holes electrically connects a metal line of one metal layer with a metal line of another metal layer. The integrated circuit chip further comprises a first tap that is located in a first one of the metal layers and a second and third tap that are located in a second one of the metal layers. The metal lines and via holes form a signal path that electrically connects the first tap with the second tap. The metal lines in each metal layer are arranged in a respective first one of at least two predefined configurations. The at least two predefined configurations comprise for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with the third tap.
In another embodiment, there is provided a method of manufacturing a metal layer structure that comprises at least three substantially horizontal metal layers and a plurality of substantially vertical via holes. Each of the metal layers comprises at least one metal line. Each of the via holes electrically connects a metal line of one metal layer with a metal line of another metal layer. The structure further comprises a first tap that is located in a first one of the metal layers, and a second and third tap that are located in a second one of the metal layers. The metal lines and via holes form a signal path that electrically connects the first tap with the second tap. The metal lines in each metal layer are arranged in a respective first one of at least two predefined configurations. The at least two predefined configurations comprise for each metal layer a second predefined configuration that arranges the metal lines in the metal layer to form, together with the via holes and the metal lines in the other metal layers, a modified signal path that electrically connects the first tap with the third tap. The method comprises selecting a metal layer of the structure, determining the predefined configuration of metal lines in the selected metal layer, selecting a different predefined configuration, preparing a layout mask for the selected metal layer according to the selected predefined configuration, and structuring a structure using the layout mask.